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| 1 of 28 032305 features direct-to-digital temper ature sensor requires no external components or user calibration two fan speed sensors monitors 6 power supply voltages 8-bit dac for fan speed control intrusion detect for security (detects when chassis lid has been removed, even if power is off) remote system reset system interrupt availability on all monitored functions (temperature, voltages, fan speed, chassis intrusion) 2-wire interface with 2-bit addressability integrated nand tree for board level testability wide power supply range (2.8v v dd 5.75v) high integration in a small 24-pin 173-mil tssop applications include monitoring of personal computers or any microprocessor-based system pin assignment pin description a0/nt out - address input / nand tree output a1 - address input sda - 2-wire serial data input/output scl - 2-wire serial clock fanx - tachometer inputs chs - chassis intrusion detector input gndd - digital ground v dd - power supply voltage (2.8v to 5.75v) int - hardware interrupt output v out /nt in - dac output / nand tree input rst - remote system reset gnda - analog ground +xxv in - positive voltage inputs +2.5v s /+v ccp2 - positive/negative voltage input vidx - processor voltage supply readout inputs see table 11 on page 27 for ordering information ds1780 cpu peripheral monito r www.dalsemi.com DS1780E+ 24-pin tssop ( 173-mil ) 23 vid0 vid vid2 vid3 vid4 +v ccp1 +2.5 v in +3.3 v in +5 v in +12 v in +2.5 v s /+v ccp2 gnda 1 2 3 4 5 6 7 8 9 10 11 12 24 22 21 20 19 18 17 16 15 14 13 sd a fan1 chs gndd v dd int v out / nt in rst a1 scl fan2 a0/nt out
ds1780 2 of 28 description the ds1780 is a highly integrated sy stem instrumentation monitor ideal for use in personal computers, or any microprocessor-based system. it monitors ambien t temperature, six power supply voltages, and the speed of two fans. fan speed can also be contro lled with the use of an internal 8-bit dac. all measurements are internally converted to a di gital format for easy processing by the cpu. the ds1780 can be reset to its default power-up state via a remote reset functi on with internal debounce and delay. it features an interrupt that can be pr ogrammed to become active should any of the functions the ds1780 is monitoring fall out of spec. for board-level testability, an internal nand tree function simplifies the system design. a chassis intrusion input is featured to enhance system security. programming and data readout are accessed via a simple 2-wire interface with 2-bit addressability. the ds1780 power supply range of 2.8v to 5.75v allows for m onitoring of parameters for 3v or 5v systems. the ds1780 is assembled in a compact 173-mil tssop package. detailed pin description table 1 pin signal direction description 1 a0/nt out digital i/o the lowest order programmable bit of the 2-wire bus address. this pin functions as an output when doing a nand tree test. 2 a1 digital input the highest order programmable bit of the 2-wire bus address. 3 sda digital i/o 2-wire bus bi-directional data. open-drain output. 4 scl digital input 2-wire bus synchronous clock. 5 fan1 digital input 0 to v dd amplitude fan tachometer input. 6 fan2 digital input 0 to v dd amplitude fan tachometer input. 7 chs digital i/o an active high input from an external circuit, which latches a chassis intrusion event. this line can go high without any clamping action regardless of the powered state of the ds1780. the ds1780 provides an internal open drain on this line, controlled by bit 6 of configuration register, to provide a minimum 20 ms reset of this signal. 8 gndd ground internally connected to all digital circuitry. 9 v dd power +3.3v or +5v v dd power. bypass with the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors. 10 int digital output active-low programmable interrupt output. the output is enabled when bit 1 of the configuration register is set to 1. the default state is disabled. 11 v out /nt in digital input/ analog output an active-high input that enables nand tree board-level connectivity testing. refer to ?nand tree testing? section. used as dac output when nand tree is not selected. 12 rst digital i/o master reset, 5 ma open drain driver, active low output with at least a 20 ms minimum pulse width. available when enabled via bit 4 in configuration register. this is a bi-directional i/o pin. it acts as power on reset input. 13 gnda ground internally connected to all analog circuitry. the ground reference for all analog inputs. 14 +2.5v s /+v ccp2 analog input analog input for monitoring -12v or +v ccp2 . ds1780 will measure voltages on this pin from 0v to 3.6v. an external resistor ladder is required for monitoring a -12v supply (see figure 1). 15-19 +xxv in analog inputs a/d inputs for 5 positive voltages. 20-24 vidx digital inputs voltage supply readouts from the processo r. these values are read in the vid and vid4 status registers. ds1780 3 of 28 overview a block diagram of the ds1780 is shown in figure 1. the ds1780 provides six analog inputs, an analog out put, five digital inputs, two fan speed inputs, a temperature sensor, and interrupt re gisters on a single chip, which co mmunicates on a 2-wire serial bus. the ds1780 performs power supply, temperature, and fan monitoring for personal computers. the analog voltages are divided internally by the ds 1780. the inputs are then converted to 8-bit digital words. the analog inputs are intended to be connected to the several power supplies present in a typical computer. temperature can be converted to a 9-b it two?s-complement digita l word with a 0.5c lsb. the analog output is approximately a 0-1.25v output from an 8-bit d/a converter, which is used to control fan speeds. fan inputs measure the period of tac hometer pulses from the fans, providing a higher count for lower fan speeds. the fan inputs are digital inputs with an acceptable range of 0 to v dd volts and a transition level of approximately 1.4 volts. full-scal e fan counts are 255 (8-bit counter) and this represents a stopped or very slow fan. nominal speeds, based on a count of 153, are programmable from 1100 to 8800 rpm on fan1 and fan2. signal conditioning circuitry is included to accommodate sl ow rise and fall times. the ds1780 provides a number of internal regist ers, as detailed in table 1. these include: configuration register: provides control and configura tion, as well as initialization. interrupt ( int ) status registers: two registers to provide status of each interrupt limit or interrupt event. interrupt ( int ) mask registers: allows masking of individual interr upt sources, as well as separate masking for the hardware interrupt output. temperature configuration register: the lower 2 bits of this register configure the type of temperature interrupt mode to be used. bit 7 reflects the lowest bit of the temperature reading. vid register, vid4 register: bits 0-3 of the vid register reflect the status of the vid0-vid3 pins, bit 0 of the vid4 register reflect the status of vid4 pin. these are simply input pins - not processed in any way. in a multiprocessor system, these signals will be multiplexed externally from the various processor sources, with the source being controlled by software. value ram: the monitoring results and limits for temper ature, voltages, and fan counts are all contained in the value ram. when the ds1780 is started, it cycles through each measurement in sequence, and it continuously loops through the sequence approximately once every sec ond. each measured value is compared to values stored in limit registers. when the measured valu e violates the programmed limit the ds1780 will set a corresponding system management interrupt (smi) in the interrupt status registers. one hardware interrupt line, int , is available to generate an smi. int is fully programmable with masking of each interrupt source, and masking of the output. in additi on, the configuration register has control bits to enable or disable the hardware interrupts. ds1780 4 of 28 a chs (chassis intrusion) digital input is provided. the chassis intrusion input is designed to accept an active high signal from an external circuit that latches when the case is removed from the computer; this pin is a dual purpose pin which will be driven lo w by the ds1780 to reset the external circuit. ds1780 functional block diagram figure 1 note: r1 and r2 on the -12v resistance ladder should be ratioed such that appr oximately +2.5v appears at the input pin (i.e., r1=4k ? , r2=23.2 k ? ). if a second processor voltage needs to be monitored (v ccp2 ), leave r2 empty, and make r1 500 ? , with v ccp2 appearing here. 2-wire serial data bus when using the 2-wire bus, a write will always consis t of the ds1780 2-wire slave address, followed by the internal address register byte, then the data byte. the internal address register addresses are listed below in table 2. there are two cases for a read: 1. if the internal address register is known to be at the desired address, simply read the ds1780 with the 2-wire slave address, followed by the data byte read from the ds1780. 2. if the internal address register value is unknown, write to the ds1780 with the 2-wire slave address, followed by the internal address register byte. then restart the serial communication with a read consisting of the 2-wire slave address, follo wed by the data byte read from the ds1780. the default power-on 2-wire slave address fo r the ds1780 is 01011(a1)(a0) binary, where a0-a1 reflects the state of the pins defined by the same names. the address can be changed by writing any desired value to the 2-wire serial address register (excluding the 2 lsbs). this communication protocol is depicted in the 2-wire timing diagrams of figures 2 and 8. ds1780 5 of 28 internal address register map table 2 register ds1780 internal hex address power on value notes configuration register 40h 0000 1000 interrupt (int) status register 1 41h 0000 0000 interrupt (int) status register 2 42h 0000 0000 interrupt (int) mask register 1 43h 0000 0000 interrupt (int) mask register 2 44h 0000 0000 chassis intrusion clear register 46h 0000 0000 bit 7 of this register clears chassis intrusion. the other bits are reserved. vid register 47h 0101 xxxx the lower 4 bits reflect the state of vid0-vid3 pins. serial address register 48h 0010 11xy x reflects state of a1 and y reflects a0 state vid4 register 49h 1000 000x bit 0 = vid 4. the rest are reserved. temperature configuration register 4bh 0000 0001 test register 15h 0000 0000 do not alter the contents of the register. analog output 19h 1111 1111 full on value ram 20h-3dh company id 3eh 1101 1010 read only stepping 3fh 0000 0001 read only ds1780 6 of 28 2-wire serial communica tion with the ds1780 figure 2 operation - power-on applying power to the ds1780 causes a reset of seve ral of the registers. power-on conditions of the registers are shown in table 2 above. some register s have indeterminate powe r-on values, such as the limit and ram registers of the value ram page, and these are not shown in the table. upon power-up the adc is inactive. writing limits into the value ram should usually be the first action performed after power up. the rst pin is bi-directional. it forces reset at power-on, but can also be pulled low to force reset internally. operation - resets the ds1780 features four distinct rese tting functions. each one has a diff erent effect on re gister contents and the state of the rst output following the event. e ach one is explained below: power-on reset - on por, all internal logic is reset, and registers are cleared to their default state (see tables 10.x). because value ram is typically the first area programmed upon power-up, it does not have a defined state upon por. also, on por, the rst output will be pulled to an active low state for 20 ms (minimum). a por occurs every time v dd crosses the voltage level approximately equivalent to the sum of one n- channel threshold (v tn ) and one p-channel threshold (v tp ), on a power-up or power-down condition. ds1780 sram contents get ?scrambled? when v dd falls below the greater of one n-channel v t or one p- channel v t . therefore, sram contents will always be in a defined state as supply voltage reaches the minimum spec level of 2.8v, even in a power supply brownout condition. ds1780 7 of 28 software reset - this condition is generated by writing a 1 to bit 4 of the configuration register. it has no effect on ds1780 register contents. it will however pull the rst output to the active low state for a duration of 20 ms (minimum). when the rst output goes active, this bit in the configuration register will clear itself. a software reset is only possible if bit 7 of the int mask register 2 (0x44h) is set to ?1?. device initialization - this condition is generated by writing a 1 to bit 7 of the configuration register. it will clear all registers in ds1780 memory to their default state except the value ram (0x20h - 0x3dh) and analog output (0x19h). these locations will remain unchanged from their state before the initialization. this condition has no effect on the rst output. this bit is self-clearing. hardware reset - this condition is generated by some external source pulling the rst pin below vin(0) (see dc electrical character istics). the ds1780 will then force the rst signal to remain in the active low state for >20 ms. it will clear all register s in ds1780 memory to their default state except the value ram (0x20h - 0x3dh) and analog output (0x 19h). these locations will remain unchanged from their state before the hardware reset. operation - configuration register control of the ds1780 is provided through the configura tion register. the configuration register is used to start and stop the ds1780, enable or disable inte rrupt output and modes, a nd provide the initialization function described above. bit 0 of the configuration regist er controls the monitoring loop of the ds1780. setting bit 0 low stops the monitoring loop and puts the ds1780 into a st andby mode. 2-wire bus communication is still possible with any register in the ds1780 during th e standby mode, however. additionally, the ds1780 will continue to monitor the rst and chs inputs while in a standby mode. setting bit 0 high starts the monitoring loop. bit 1 of the configuration register enables or disables the int interrupt output. setting bit 1 high enables the int output, setting bit 1 low disables the output. bit 3 of the configuration register is used to clear the int interrupt output when set high. the ds1780 monitoring function will stop until bit 3 is set low. interrupt status register contents will not be affected. bit 4 of the configuration register is used to initiate a minimum 20 ms reset signal on the rst output if the pin is configured for the reset mode (via bit 7 of the int mask register 2 - 0x44h). bit 6 of the configuration register is used to rese t the chassis intrusion (chs) output pin when set high. bit 7 of the configuration register is used to start a configuration register initialization when taken high, as described in the ?operation - resets? section. operation - monitoring loop the ds1780 monitoring function is started by doing a write to the configurati on register and setting the int_clear (bit 3) low, and start (bit 0) high. at this point the int_enable (bit 1) should be set high to enable interrupts (int). the ds1780 then performs a ?round robin? sampling of the inputs, sampling each approximately once a second, in the order (co rresponding to locations in the value ram) shown below in table 3. the results of the sampling and conversions can be found in the value ram (table 10.13) and are available at any time. ds1780 8 of 28 ds1780 monitoring order table 3 temperature reading analog +2.5 v s /v ccp2 analog +12v analog +5v analog +3.3v analog +2.5v analog +v ccp1 fan1 fan2 if conversions are terminated by either of the methods described in the ?operation - configuration register? section, the current ?round-robin? loop will be completed and the results stored in ram. monitoring will then terminate. when the monitoring again commences, monitoring always starts with the temperature reading. operation - temperature data format the ds1780 internally converts measured temperature data to a two?s co mplement data format (in c). the host can read the last completed temperature c onversion at any time by setting the internal address register pointer to location 27h, and reading the 8 bits in the register. the format of the data is shown below in table 4. the msb of the register represents the sign bit of the temperature reading. for fahrenheit usage, a lookup table or conversion routine must be used. temperature/data relationships table 4 s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb (unit = c) lsb temperature digital output (binary) digital output (hex) +125c 0111 1101 7dh +25c 0001 1001 19h +1c 0000 0001 01h 0c 0000 0000 00h -1c 1111 1111 ffh -25c 1110 0111 e7h -40c 1101 1000 d8h operation - voltage data format the ds1780 contains inputs for direct ly monitoring the power supplies typically found in a pc (+12v, - 12v, +5v, +3.3v, +2.5v, +v ccp ). these inputs are scaled internally to a reference source, and converted via an 8-bit delta-sigma adc (analo g-to-digital converter), thus allowi ng for a more accurate means of measurement since the voltages are referenced to a known value. since these inputs can be greater than v dd , they are not diode protected to the power rails. in addition, small external series resistors such as 510 ? should be put into the lines driving the ds1780 to prevent damaging the traces or power supplies should an acci dental short connect two power supplies together. ds1780 9 of 28 the worse such accident would be connecting -12v to +12v; a total of 24v difference, with the series resistors this would draw a ma ximum of approximately 24 ma. the internal scaling factor depends upon the particular input. the +12v in , +5v in , +3.3v in , and +2.5v in inputs are internally scaled such that the nominal va lue of the respective supply corresponds to 3/4 of full range, or a decimal count of 192. the ap proximate resolution is thus equal to: lsb (v nom ) 256 v 4/3 nom this is depicted below in table 5. voltage/data relation ships for positive only voltage inputs (+12v in , +5v in , +3.3v in , and +2.5v in ) table 5 input pin +12v in +5v in +3.3v in +2.5v in lsb weighting (mv) 62.5 26.0 17.2 13.0 adc result (base 10) pin voltage (v) pin voltage (v) pin voltage (v) pin voltage (v) 0 0 0 0 0 1 0.063 0.026 0.017 0.013 2 0.125 0.052 0.034 0.026 3 0.188 0.078 0.052 0.039 4 0.25 0.104 0.069 0.052 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 190 11.875 4.948 3.266 2.474 191 11.938 4.974 3.283 2.487 192 12.0 5.0 3.3 2.5 193 12.063 5.026 3.317 2.513 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 252 15.75 6.563 4.331 3.281 253 15.813 6.589 4.348 3.294 254 15.875 6.615 4.366 3.307 255 15.938 6.641 4.383 3.32 the other two voltage inputs use a slightly different s caling technique, due to the nature of the pc voltage they are monitoring. because processor voltage (v ccp ) can vary to 3.6v, the +v ccp1 and +2.5v s /+v ccp1 inputs are internally scaled such that the adc result is 0h for a 0v input and the maximum value of ffh is returned for a voltage of 3.60v. this corresponds to an lsb weighting of 14.1 mv. the inputs can also be used to monitor a negative suppl y, such as -12v. however, a resistor ladder and positive reference voltage (v ref ) must be used (see figure 1) su ch that input voltage to the ds1780 swings between ov and +3.6v. assuming the ds1780 +v ccp1 and +2.5v s /+v ccp2 pins have infinite input impedance and the v ref is a perfect supply, then the resolution and range of -12v input are: lsb (r 1 , r 2 ) 255 3.6 1 2 1 r r r ds1780 10 of 28 v min (v ref , r 1 , r 2 ) - 1 2 r r v ref v max (v ref , r 1 , r 2 ) v ref -(v ref -3.6) 1 2 1 r r r if the +2.5v s /+v ccp2 is to be used to monitor a secondary processor core voltage (v ccp2 ), r2 should be removed and r1=500 ? . table 6 below shows the voltage/data re lationship for these inputs in the ideal case. in this example, v ref =+5.0v, r1=4.0 k ? , and r2=23.2 k ? . analog inputs will provide best accuracy when refe rred to the gnda pin. a separate, low-impedance ground plane for analog ground, which provides a ground point for the voltage dividers and analog components will provide best performance but is not mandatory. analog components such as voltage dividers should be located physically as close as possible to the ds1780. the power supply bypass, the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors connected between pin 9 and ground, should also be located as close as possible to the ds1780. voltage/data rela tionships for v ccp voltage inputs (+v ccp1 , +2.5vs/ +v ccp2 ) table 6 input pin +v ccp1 +2.5v s /+v ccp2 lsb weighting (mv) 14.1 96.0 (used to monitor v ccp ) (used to monitor -12v) adc result (base 10) pin voltage (v) supply voltage (v) 0 0 -29.0 1 0.014 -28.90 2 0.028 -28.81 3 0.042 -28.71 4 0.056 -28.62 ? ? ? ? ? ? ? ? ? 136 1.920 -15.94 137 1.934 -15.85 138 1.948 -15.75 139 1.962 -15.66 ? ? ? ? ? ? ? ? ? 252 3.558 -4.808 253 3.572 -4.712 254 3.586 -4.616 255 3.60 -4.52 operation - fan speed data format inputs are provided for signals from fans equipped w ith tachometer outputs. these are logic-level inputs with an approximate threshold of 1.4v. signal conditioning in the ds1780 accommodates the slow rise and fall times typical of fan tachometer outputs. the maximum input signal range is 0 to v dd . in the event these inputs are supplied from fan outputs which exceed 0 to v dd , either resistive division or diode clamping must be included to keep inputs within an acceptable range, as shown in figure 3. r2 is selected so that it does not develop excessive voltage du e to input leakage. r1 is selected based on r2 to provide a minimum input of 2v and a maximum of v dd . r1 should be as low as possible to provide the ds1780 11 of 28 maximum possible input up to v dd for best noise immunity. alternativ ely, use a shunt reference or zener diode to clamp the input level. tables 7 and 8 describe the format of the data st ored in the fan reading registers (internal address registers 28h and 29h). fan tachometer input options figure 3 voltage/data relationships for fan inputs (fan1, fan2) under default (2) mode table 7 rpm timer per revolution counts for ?divide by 2? (default mode) in decimal comments 4400 13.64 ms 153 typical rpm 3080 19.48 ms 219 70% rpm 2640 22.73 ms 255 (maximum) 60% rpm voltage/data relati onships for fan inputs (fan1, fan 2) table 8 mode select nominal rpm time per revolution counts for the nominal speed in decimal 70% rpm time per revolution for 70% rpm divide by 1 8800 6.82 ms 153 6160 9.74 ms divide by 2 4400 13.64 ms 153 3080 19.48 ms divide by 4 2200 27.27 ms 153 1540 38.96 ms divide by 8 1100 54.54 ms 153 770 77.92 ms in general, the value stored in the fan registers (in decimal) follows the equation: count (rpm, divisor) divisor rpm 10 x 1.35 6 if fans can be powered while the power to the ds1780 is off, the ds1780 inputs will provide diode clamping. limit input current to the input current at any pin specification shown in the absolute maximum ratings section. in most cases, open coll ector outputs with pullup resistors inherently limit this current. if this maximum current could be ex ceeded, either a larger pullup resistor should be used or resistors connected in series with the fan inputs. the fan inputs gate an internal 22.5 khz oscillator for one period of the fan signal into an 8-bit counter (maximum count = 255). the default divisor, located in the fan divisor/rst_register, is set to 2 (choices are 1, 2, 4, and 8) providing a nominal count of 153 for a 4400 rpm fan with two pulses per revolution. typical practice is to consider 70% of nor mal rpm a fan failure, at which point the count will be 219. ds1780 12 of 28 operation - interrupts an external interrupt can come from the following sources. while the label suggests a specific type or source of interrupt, this label is not a restriction on the usage; it could come from any desired source. 1. analog voltage: an interrupt will be generated if a analog voltage high or low limit has been exceeded; this is generally when a power s upply is out of its normal operating range. 2. temperature: an interrupt will be generated if a high or a low hot temperature limit has been exceeded. 3. fan speed: an interrupt will be generated if a fan count limit has been exceeded. 4. chassis intrusion: this is an active high interrupt from any type of device that detects and captures chassis intrusion violations. this could be accomplished mechanically, optically, or electrically, and circuitry external to the ds1780 is expected to latch the event. all system management interrupts (smis) are indicated in the two interrupt status registers. the int output has individual mask register s and individual masks for each interrupt. as described in the ?operation - configuration regi ster? section, this hardware interrupt line can also be enabled/disabled in the configuration register. reading an interrupt status register will output the contents of the register, and reset the register. a subsequent read done before the analog ?round-robin? monitoring loop is comple te will indicate a cleared register. allow at least 1 second to allow all regi sters to be updated between reads. in summary, the interrupt status register clears upon being read, and requires at least 1 second to be updated. when the interrupt status register clears, the hardwire interrupt line will also clear until the registers are updated by the monitoring loop. the int hardware interrupt output is cleared with the int_clear bit, which is bit 3 of the configuration register, without affecting the contents of the inte rrupt status registers. when this bit is high, the ds1780 monitoring loop will stop. it will resume when the bit is low. analog voltage limits the limits for the analog voltage comparison are programmed into the value ram at internal address registers 2bh - 36h. a high and low limit is associated with each of the 6 analog voltage inputs of the ds1780. care must be taken to progr am the limit registers in the same format as the respective voltage data register. please see ?operation - voltage data format? for details. for setting a voltage interrupt, the ds1780 compares on a ?greater than? ba sis for high limits and a ?less than or equal to? basis for low limits. the host can mask any or a ll of the voltage limits fo r interrupt contention. temperature limits and interrupt modes the host programs an 8-bit high temperature limit a nd hysteresis/low temperature limit into the ds1780 at internal address registers 39h and 3 ah in the same two?s complement format described in the ?operation - temperature data format? section. the temperature mode is programmed into the temperature configuration register (0x4bh). a digital 8-bit comparator is also incorporated that compares the temperature readings to the programmed limits. there are three interrupt modes of operation. the int output can be programmed for either of the three interrupt modes of opera tion and the host can program the ds1780 to completely mask temperature interrupts from controlling the int output. ds1780 13 of 28 1. one-time interrupt mode: exceeding hot temperature limit causes an smi that will remain active indefinitely until reset by reading interrupt status register 1 or cleared by the int_clear bit in the configuration register. once an smi event has occurred by crossing the hot temperature limit, then subsequently reset, an smi will not occur again until the temperature goes below hot temperature hysteresis (low) limit. 2. default interrupt mode: exceeding hot temperature limit causes an system management interrupt (smi) that will remain active indefinitely until reset by reading interrupt status register 1 or cleared by the int_clear bit in the configuration register. once an interrupt event has occurred by crossing the hot temperature limit, then reset, an interrupt will occur again once the next temperature conversion has completed. the interrupts will continue to occur in this manner until the temperature goes below the hot temperature hysteresis value. 3. comparator mode: exceeding hot temperature limit causes the smi output to go active. smi will remain active until the temperature goes below the hot temperature limit. once the temperature goes below the hot temperature limit, smi will become inactive. as in the default and one-time interrupt modes, the smi can also be cleared by reading inte rrupt status register 1 or by setting the int_clear bit in the configuration register. figure 4 below illustrates the three temperature interrupt modes. fan speed limits the host programs 8-bit fan speed low limits for fan1 and fan2 inputs into internal address registers 3bh and 3ch, respectively. care must be taken to program the limit with respect to the divisor chosen for each of the tachometer inputs. refer to the ?opera tion - fan speed data format? section for details. an interrupt will occur if measured fan speed falls below the programmed limit. due to the nature of the algorithm implemented, a count of 255 (max) represents a slow (or stopped) fan; i.e., tachometer counts are inversely proportional to fan speed. thus, the fa n limit register will contain the maximum number of counts (or the minimum fan speed) before which an interrupt will occur. chassis intrusi on detection the chs input is an active high interrupt from any type of device that de tects and captures chassis intrusion violations. this could be accomplished mechanically, optically, or electrically, and circuitry external to the ds1780 is expected to latch the event. the design of the ds1780 allows this input to go high even with no power applied to the ds1780, and no clamping or other interference with the line will occur. this line can also be pulled low for at least 20 ms by the ds1780 to reset a typical chassis intrusion ci rcuit. accomplish this reset by setting bit 6 of configuration register high. the bit in the register is self-clearing. a possible chassis intrusion detector /latch is shown below in figure 5. ds1780 14 of 28 temperature interrupt mode illustration figure 4 sample chassis intrusion detector/latch figure 5 ds1780 15 of 28 operation - analog output the ds1780 has a single analog output from a unsigned 8-bit d/a which produces 0-1.25 volts; this is amplified and scaled with external circuitry such as a op-amp and transistor to provide fan speed control. this register is set to 0xff on power-up, which produ ces full fan speed. the analog output register (19h) is unaffected by any reset other than power-on. this voltage must be scaled and have an output curre nt of at least 250 ma which is needed to drive the fans; figure 6 is a simple circuit that can be us ed, and table 9 suggest r1 and r2 to select gain. although it is recommended to connect the ds1780 anal og output to a high impedance node such as that in figure 6, the output driver can source 2.0 ma (max) at v out = 1.25v while maintaining the error spec of 5% of fsr over temperature a nd supply voltage. stability is guaranteed for a load capacitance up to 100 pf. more capacitance could cause se vere overshoots and possible oscillation. fan amplifier circuit example figure 6 amplifier design examples table 9 input 1.22 output 12 gain 9.84 r1 r2 1,000 9,000 2,200 19,439 3,300 29,159 4,700 41,530 10,000 88,361 operation - nand tree test a nand tree is provided in the ds1780 for automated test equipment (ate) bo ard level connectivity testing. if the user applies (v dd - 0.5v) to the nt in input, the device will be in the nand tree test mode. a0/nt out will become the nand tree output pin. to perf orm a nand tree test all pins included in the nand tree (see figure 7 below) should be driven high. beginning with a1 and working around the chip, each pin can be toggled and a resulting toggle can be observed on a0/nt out . allow for a typical propagation delay of 100 ns. ds1780 16 of 28 note: to properly implement the nand tree test on th e pcb, no pins listed in the tree should be connected directly to power or ground; if a pin is n eeded to configure as a permanent low such as an address, it should be connected to ground through a low value resister such as 330 (to allow the ate (automatic test equipment) to drive it high. ds1780 nand tree test flow figure 7 ds1780 registers and ram internal address register table 10.0 bit name r/w description <7:0> address pointer w addre ss of ram and registers. see the tables below for detail. address pointer (power on default 00h) table 10.1 registers and ram ds1780 17 of 28 configuration register (address 0x40; power-up default = 08h) table 10.2 bit name r/w description 0 start r/w logic 1 enables startup of measurement loop, logic 0 places the ds1780 in standby mode. caution: the int output pin will not be cleared if the user writes a 0 to this location after an interrupt has occurred (see ? int clear? bit). at startup, limit checking functions and scanning begins. note, all high and low limits should be set into the ds1780 prior to turning on this bit. (power-up default=0). 1 int enable r/w logic 1 enables the int output. 1=enabled 0=disabled (power-up default = 0) 2 reserved r/w power-up default = 0. 3 int clear r/w during interrupt service routine (isr) this bit asserted logic 1 clears int output without affecting the contents of the interrupt status registers. the device will stop monitoring. it will resume upon clearing of this bit. (power-up default=1.) 4 reset r/w creates a reset (active low) signal for 20 ms (min) on the rst output. (power-up default = 0) this bit is cleared once the rst pulse goes active. 5 reserved r/w power-up default = 0. 6 chs reset r/w logic 1 resets the chassis intrusion pin. (power-up default = 0) this bit is cleared after chs becomes cleared. 7 initialization r/w logic 1 restores power-up default values to all ds1780 registers except for the analog output and value ram, which remain unchanged. this bit automatically clears itself since the power on default is 0. interrupt int status register 1 (address 0x41; power-up default = 00h) table 10.3 bit name r/w description 0 +2.5v_error r a 1 indicates a high or low limit has been exceeded. 1 v ccp1 _errror r a 1 indicates a high or low limit has been exceeded. 2 +3.3v_error r a 1 indicates a high or low limit has been exceeded. 3 +5v_error r a 1 indicates a high or low limit has been exceeded. 4 temp_error r a 1 indicates that a high or low temperature limit has been exceeded. the conditions that will generate and clear this bit depend upon the temperature interrupt mode chosen. the mode is set at bits 0 and 1 of the temperature configuration register (0x48h). 5 reserved r 0 6 fan1_error r a 1 indicates that a fan count limit has been exceeded. 7 fan2_error r a 1 indicates that a fan count limit has been exceeded. ds1780 18 of 28 interrupt int status register 2 (address 0x42; power-up default=00h) table 10.4 bit name r/w description 0 +12v_error r a 1 indicates a high or low limit has been exceeded. 1 -12v/ v ccp2 _error r a 1 indicates a high or low limit has been exceeded. 2 reserved r 0 3 reserved r 0 4 chassis_error r a 1 indicates chassis intrusion has gone high. 5 reserved r 0 6 reserved r 0 7 reserved r 0 note: anytime the int status registers are read out, the conditions (i.e., registers) that are read are automatically reset to power-up state (except chs, which can only be cleared by chs reset). in the case of the voltage priority indication, if two or mo re voltages were out of limits, then another indication would automatically be generated if it were not handled during the isr. the errant voltage may be masked until the operator has time to clear the erra nt condition or set the limit higher/lower. int mask register 1 (address 0x43; power-up default=00h) table 10.5 bit name r/w description 0 +2.5v r/w a 1 disables the corresponding interrupt status bit for int interrupt. 1 +v ccp1 r/w a 1 disables the corresponding interrupt status bit for int interrupt. 2 +3.3v r/w a 1 disables the corresponding interrupt status bit for int interrupt. 3 +5v r/w a 1 disables the corresponding interrupt status bit for int interrupt. 4 temp r/w a 1 disables the corresponding interrupt status bit for int interrupt. 5 reserved r/w power on default = 0. 6 fan1 r/w a 1 disables the corresponding interrupt status bit for int interrupt. 7 fan2 r/w a 1 disables the corresponding interrupt status bit for int interrupt. int mask register 2 (address 0x44; power-up default=00h) table 10.6 bit name r/w description 0 +12v r/w a 1 disables the corresponding interrupt status bit for int interrupt. 1 -12v/v ccp2 r/w a 1 disables the corresponding interrupt status bit for int interrupt. 2 reserved r/w power-up default = 0. 3 reserved r/w power-up default = 0. 4 chs_sec (chassis intrusion) r/w a 1 disables the corresponding interrupt status bit for int interrupt. 5 reserved r/w power-up default = 0. 6 reserved r/w power-up default = 0. 7 reset enable r/w a 1 enables the reset in the configuration register. ds1780 19 of 28 reserved register (address 0x 45; power-up default=00h) table 10.7 bit name r/w description <7:0> reserved r/w undefined (power on = 00h). chassis intrusion clear regi ster (address 0x46; power-up default=00h) table 10.8 bit name r/w description 0-6 reserved r/w undefined (power on = 00h). 7 chassis int clear r/w a 1 outputs a minimum 20 ms active low pulse on the chassis intrusion (chs) pin. the register bit clears itself after the pulse has been output. vid register (address 0x47; power-up default = see ?address pointer? table) table 10.9 bit name r/w description 0-3 vid r the vid[3:0] inputs from pentium/pro power supplies to indicate the operating voltage (e.g., 1.5v to 2.9v). 4-5 fan1 rpm control r/w fan1 speed control. <5:4> = 00 - divide by 1 <5:4> = 01 - divide by 2 <5:4> = 10 - divide by 4 <5:4> = 11 - divide by 8 6-7 fan2 rpm control r/w fan2 speed control. <7:6> = 00 - divide by 1 <7:6> = 01 - divide by 2 <7:6> = 10 - divide by 4 <7:6> = 11 - divide by 8 serial address register (address 0x48; power-up default = see description below) table 10.10 bit name r/w description 0-7 2-wire bus address r/w 2-wire bus address (power on = 001011(a1)(a0)). vid4 register (address 0x49; power-up default = see description below table 10.11 bit name r/w description 0 vid 4 r vid4 input. 1-7 reserved r/w default power on values = 1000000. ds1780 20 of 28 temperature configuration register (address ox4b; power-up default = 01h) table 10.12 bit name r/w description 0 hot temperature interrupt mode select bit 0 r/w if bits 0 and bits 1 of this register are both 0 or both 1, this selects the default interrupt mode which gives the user an interrupt if the temperature goes above the hot limit. the interrupt will be cleared once the status register is read, but it will again be generated when the next conversion has completed. it will continue to do so until the temperature goes below the hysteresis limit. a 0 on bit 1 and a 1 on bit 0 selects the one-time interrupt mode which gives the user an indefinite interrupt when it goes above the hot limit. the interrupt will be cleared once the status register is read. another interrupt will not be generated until the temperature first goes below the hysteresis limit. it will also be cl eared if the status register is read. no more interrupts will be generated until the temperature goes above the hot limit again. the corresponding bit will be cleared in the status register every time it is read but may not set again when the next conversion is done. 1 hot temperature interrupt mode select bit 1 r/w a 1 on this bit (bit 1) and a 0 on bit 0 selects the comparator mode. this gives an smi when the temperature exceeds the hot limit. this smi remains active until the status register is read or the temperature goes below the hot limit (no hysteresis), when the smi will become inactive. 2-6 reserved r/w default = 00000. 7 temp [0] r ninth bit of the temperature (value = 0.5c). test register (address 0x15h ; power-up default = 00h) table 10.13 address ds1780 21 of 28 value ram (address 0x15h - 0x3dh) table 10.15 address ds1780 22 of 28 4. this register will latch an 8-bit value into an r-2r d/a to provide a rang e of 0-1.25 volts; accuracy can be 5% or more. 5. this location will contain the company identification number which will be used by software to determine analog voltage curves; this register is read only. 6. this location will contain the stepping number of the part; this register is read only. absolute maximum ratings* voltage on v dd (gndd-0.3v) to +6.5v voltage on any other pin (except analog inputs) (gndd-0.3v) to (v dd + 0.3v) voltage at +12v in pin (gndd-0.3v) to 18v voltage at other analog i nput pins (gndd-0.3v) to 7.0v ground difference (gndd-gnda) 0.3v input current at any pin (note 2) 5 ma package input current (note 2) 20 ma operating temperature -40c to +125c storage temperature -65c to +150c esd susceptibility (human body model) 2kv soldering temperature (note 3) 215c for 60 seconds (vapor phase) 220c for 15 seconds (ir) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. the dallas semiconductor ds1780 is built to the high est quality standards and manufactured for long term reliability. all dallas semiconductor devices are made us ing the same quality materials and manufacturing methods. however, the ds1780 is not expos ed to environmental stresses, such as burn-in, that some industrial applications require. for specific reliability in formation on this product, please contact the factory in dallas at (972) 371-4448. recommended dc operating conditions (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes supply voltage v dd 2.8 5.75 v ground difference ? gnd igndd- gndai 0.1 v digital input voltage v ind -0.05 v dd +0.05 v ds1780 23 of 28 dc electrical characteristics power supply (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes active adc and dac, interface inactive 0.7 1.0 ma adc, dac and interface inactive 125 a supply current i dd inactive adc and interface, dac active 250 500 a 4, 5 dc electrical characteristics: temperature-to-digital converter (-40 c to +125 c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes -40c ta 125c 3 thermometer error t err -25c ta 100c 2 c resolution 0.5 c dc electrical characteristics: voltage-to-digit al converter (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes adc resolution 8 bits +2.5v in input 13.0 +3.3v in input 17.2 +5v in input 26.0 +12v in input 62.5 +v ccp1,2 inputs 14.1 voltage to digital conversion resolution (see voltage a/d section) +2.5v s input 64.0 mv 0c ta 100c 1.5 % 6 total adjusted error tue -40c ta +125c 2 differential nonlinearity dnl 1 lsb power supply sensitivity pss 1 %/v monitoring cycle t c 0.5 1.0 s 7 input resistance r in 500k 750k ? ds1780 24 of 28 dc electrical characteristics: fan rpm-to-digital converter (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes 0c ta 100c 6 accuracy -40c ta +125c 12 % full scale count 255 decimal divisor=1; fan count=153 8800 divisor=2; fan count=153 4400 divisor=4; fan count=153 2200 fan1 & fan2 normal input rpm divisor=8; fan count=153 1100 rpm 8 internal oscillator frequency +25c ta +75c 21.15 22.5 23.85 khz dc electrical characteristics: analog output v out (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes dac resolution 8 bits voltage range 0 1.25 v error dac err 5 % of fsr output current i out 2.0 ma load capacitance c load 100 pf dc electrical characteristics: digital outputs: a0nt out (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes i out =5 ma at v dd =4.25v logical ?1? output voltage v out (1) i out =3 ma at v dd =2.85v 2.4 v i out =5 ma at v dd =5.75v logical ?0? output voltage v out (0) i out =3 ma at v dd =3.45v 0.4 v ds1780 25 of 28 dc electrical characteristics: open-drain digital outputs: rst , chs, int (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes i out =5 ma at v dd =5.75v logical 0 output voltage v out (0) i out =3 ma at v dd =3.45v 0.4 v high level output current i oh v out =v dd 0.1 100 a active pulse width rst and chs 20 45 ms dc electrical characteristics: open-drain 2-wire bus output: sda (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes i out =5 ma at v dd =5.75v logical 0 output voltage v out (0) i out =3 ma at v dd =3.45v 0.4 v high level output current i oh v out =v dd 0.1 100 a dc electrical characteristics: 2-wire bus digital inputs: sda, scl (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes logical 1 input voltage v in (1) 0.7v dd v logical 0 input voltage v in (0) 0.3v dd v dc electrical characteristics: digital inputs: a0/nt out , a1, chs, vid0-4, fan1, fan2 (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes logical 1 input voltage v in (1) v dd =5.0v 2.4 v logical 0 input voltage v in (0) v dd =5.0v 0.8 v logical 1 input voltage v in (1) v dd =3.3v 2.0 v logical 0 input voltage v in (0) v dd =3.3v 0.4 v ds1780 26 of 28 dc electrical characteristics: all digital inputs (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes logical 1 input current i in (1) v in =v dd -1 -0.005 a logical 0 input current i in (0) v in =0v 0.005 1 a input capacitance c in 20 pf ac electrical characteristics: 2-wire interface (-40c to +125c, 2.8v v dd 5.75v) parameter symbol condition min typ max units notes scl clock period t 1 2.5 s data in setup time to scl high t 2 100 ns data out stable after scl low t 3 0 ns sda low setup time to scl low (start) t 4 100 ns sda high hold time after scl high (stop) t 5 100 ns ds1780 27 of 28 2-wire bus timing diagram figure 8 notes: 1. all voltages are referenced to ground, unless otherwise specified. when the input voltage (vin) at any pin exceeds the power supplies (v in < (gnd or gnda) or v in >v dd , except for analog voltage inputs), the current at that pin should be limited to 5 ma. the 20 ma maximum package input current rating limits the numbe r of pins that can safely exceed the power supplies with an input current of 5 ma to four. 2. solder according to ipc standards. 3. idd specified with open-drain output pin open. 4. idd specified with v cc at 5.0v and sda, scl = 5.0v. 5. tue (total unadjusted error) includes offs et, gain and linearity errors of the adc. 6. monitoring cycle time includes temperature conversion, voltage conve rsions, and fan speed readings. 7. the total fan count is based on 2 pulses pe r revolution of the fan tachometer output. 8. limits (min and max specs) are defined for the full temperature range -40c t a +125c and voltage range 2.8v v dd 5.75v, unless otherwise stated as a condition. typical values represent parametric norms at t a = 25c at 4.5v v dd 5.5v, unless otherwise stated as a condition. ordering information table 11 ordering number package marking description DS1780E+ ds1780 (see note) ds1780 in lead-free 24-pin tssop DS1780E+t&r ds1780 (see note) ds1780 in lead-free 24-pin tssop, 1000 piece tape-and- reel DS1780E ds1780 ds1780 in 24-pin tssop DS1780E/t&r ds1780 ds1780 in 24-pin tssop, 1000 piece tape-and-reel note : a "+" symbol will also be marked on the package near the pin 1 indicator ds1780 28 of 28 ds1780 24 ld. tssop dim min max a - 1.10 a1 0.05 - a2 0.75 1.05 c 0.09 0.18 phi 0 8 l 0.50 0.70 e1 0.65 bsc b 0.18 0.30 d 7.55 8.00 e 4.40 nom g 0.25 ref h 6.25 6.55 n otes: 1. dimension ?d? includes mold missmatch, flash, and protrusions. |
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